1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to a analog-to-digital converter having a reduced number of quantizer output levels.
2. Background of the Invention
Delta-sigma modulators are in widespread use in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), in which they provide very linear behavior and simple implementation due to the reduced number of bits used in the analog signal comparison. Delta-sigma modulators can be implemented with a high level of control of the frequency distribution of “quantization noise”, which is the difference between the ideal output value of the modulator as determined by the input signal and the actual output of the modulator provided by a quantizer. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable.
The delta-sigma modulator based analog-to-digital converter includes a loop filter that receives an input signal and a quantizer that converts the output of the loop filter to a digital representation. Feedback from the quantizer output is applied to the loop filter in feedback modulator topologies or is summed with the output of the loop filter in feed-forward modulator topologies to provide a closed-loop that causes the time-average value of the output of the quantizer to accurately represent the value of the modulator input signal. The loop filter provides shaping of the quantization noise at the output of the quantizer in response to the feedback signal applied from the quantizer to the loop filter. The feedback provided from the quantizer is typically generated by a coarse feedback DAC that receives the digital output of the quantizer and generates an analog value that is provided to the loop filter or the output summer.
Present-day converters typically use multi-bit designs, in that the output of the quantizer is a multi-level signal and the coarse feedback DAC output is therefore also a multi-level signal. The multi-bit implementation provides for improved noise shaping capability and linearity of the converter and generally reduces the linearity and slew-rate requirements of the analog components in the loop filter. Therefore, multi-bit topologies are very desirable, but incur the penalty of a more complex feedback DAC and the consequent increased power consumption. Further, the linearity of the feedback DAC produces a direct effect on the linearity of the converter, as any non-linearity in the feedback DAC will be reflected in the time-average output of the quantizer that represents the input signal. If there is a greater number of bits in the feedback DAC, then it is more difficult to maintain linearity over component and environmental variations. Therefore, the number of levels provided from the quantizer output has a direct impact on ADC performance. The quantizer complexity and power consumption are also functions of the number of bits required to represent the quantizer output.
Therefore, it would be desirable to provide an ADC using a delta-sigma modulator having a reduced number of quantizer output levels.